cudaDevAttrMaxThreadsPerBlock

< Maximum number of threads per block

< Maximum block dimension X

< Maximum block dimension Y

< Maximum block dimension Z

< Maximum grid dimension X

< Maximum grid dimension Y

< Maximum grid dimension Z

< Maximum shared memory available per block in bytes

< Memory available on device for __constant__ variables in a CUDA C kernel in bytes

< Warp size in threads

< Maximum pitch in bytes allowed by memory copies

< Maximum number of 32-bit registers available per block

< Peak clock frequency in kilohertz

< Alignment requirement for textures

< Device can possibly copy memory and execute a kernel concurrently

< Number of multiprocessors on device

< Specifies whether there is a run time limit on kernels

< Device is integrated with host memory

< Device can map host memory into CUDA address space

< Compute mode (See ::cudaComputeMode for details)

< Maximum 1D texture width

< Maximum 2D texture width

< Maximum 2D texture height

< Maximum 3D texture width

< Maximum 3D texture height

< Maximum 3D texture depth

< Maximum 2D layered texture width

< Maximum 2D layered texture height

< Maximum layers in a 2D layered texture

< Alignment requirement for surfaces

< Device can possibly execute multiple kernels concurrently

< Device has ECC support enabled

< PCI bus ID of the device

< PCI device ID of the device

< Device is using TCC driver model

< Peak memory clock frequency in kilohertz

< Global memory bus width in bits

< Size of L2 cache in bytes

< Maximum resident threads per multiprocessor

< Number of asynchronous engines

< Device shares a unified address space with the host

< Maximum 1D layered texture width

< Maximum layers in a 1D layered texture

< Maximum 2D texture width if cudaArrayTextureGather is set

< Maximum 2D texture height if cudaArrayTextureGather is set

< Alternate maximum 3D texture width

< Alternate maximum 3D texture height

< Alternate maximum 3D texture depth

< PCI domain ID of the device

< Pitch alignment requirement for textures

< Maximum cubemap texture width/height

< Maximum cubemap layered texture width/height

< Maximum layers in a cubemap layered texture

< Maximum 1D surface width

< Maximum 2D surface width

< Maximum 2D surface height

< Maximum 3D surface width

< Maximum 3D surface height

< Maximum 3D surface depth

< Maximum 1D layered surface width

< Maximum layers in a 1D layered surface

< Maximum 2D layered surface width

< Maximum 2D layered surface height

< Maximum layers in a 2D layered surface

< Maximum cubemap surface width

< Maximum cubemap layered surface width

< Maximum layers in a cubemap layered surface

< Maximum 1D linear texture width

< Maximum 2D linear texture width

< Maximum 2D linear texture height

< Maximum 2D linear texture pitch in bytes

< Maximum mipmapped 2D texture width

< Maximum mipmapped 2D texture height

< Major compute capability version number

< Minor compute capability version number

< Maximum mipmapped 1D texture width

< Device supports stream priorities

< Device supports caching globals in L1

< Device supports caching locals in L1

< Maximum shared memory available per multiprocessor in bytes

< Maximum number of 32-bit registers available per multiprocessor

< Device can allocate managed memory on this system

< Device is on a multi-GPU board

< Unique identifier for a group of devices on the same multi-GPU board

< Link between the device and the host supports native atomic operations

< Ratio of single precision performance (in floating-point operations per second) to double precision performance

< Device supports coherently accessing pageable memory without calling cudaHostRegister on it

< Device can coherently access managed memory concurrently with the CPU

< Device supports Compute Preemption

< Device can access host registered memory at the same virtual address as the CPU

< Device supports launching cooperative kernels via ::cudaLaunchCooperativeKernel

< Device can participate in cooperative kernels launched via ::cudaLaunchCooperativeKernelMultiDevice

< The maximum optin shared memory per block. This value may vary by chip. See ::cudaFuncSetAttribute

< Device supports flushing of outstanding remote writes.

< Device supports host memory registration via ::cudaHostRegister.

< Device accesses pageable memory via the host's page tables.

< Host can directly access managed memory on the device without migration.