CU_DEVICE_ATTRIBUTE_MAX_THREADS_PER_BLOCK

< Maximum number of threads per block

< Maximum block dimension X

< Maximum block dimension Y

< Maximum block dimension Z

< Maximum grid dimension X

< Maximum grid dimension Y

< Maximum grid dimension Z

< Maximum shared memory available per block in bytes

< Deprecated, use CU_DEVICE_ATTRIBUTE_MAX_SHARED_MEMORY_PER_BLOCK

< Memory available on device for __constant__ variables in a CUDA C kernel in bytes

< Warp size in threads

< Maximum pitch in bytes allowed by memory copies

< Maximum number of 32-bit registers available per block

< Deprecated, use CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_BLOCK

< Typical clock frequency in kilohertz

< Alignment requirement for textures

< Device can possibly copy memory and execute a kernel concurrently. Deprecated. Use instead CU_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT.

< Number of multiprocessors on device

< Specifies whether there is a run time limit on kernels

< Device is integrated with host memory

< Device can map host memory into CUDA address space

< Compute mode (See ::CUcomputemode for details)

< Maximum 1D texture width

< Maximum 2D texture width

< Maximum 2D texture height

< Maximum 3D texture width

< Maximum 3D texture height

< Maximum 3D texture depth

< Maximum 2D layered texture width

< Maximum 2D layered texture height

< Maximum layers in a 2D layered texture

< Deprecated, use CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_WIDTH

< Deprecated, use CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_HEIGHT

< Deprecated, use CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LAYERED_LAYERS

< Alignment requirement for surfaces

< Device can possibly execute multiple kernels concurrently

< Device has ECC support enabled

< PCI bus ID of the device

< PCI device ID of the device

< Device is using TCC driver model

< Peak memory clock frequency in kilohertz

< Global memory bus width in bits

< Size of L2 cache in bytes

< Maximum resident threads per multiprocessor

< Number of asynchronous engines

< Device shares a unified address space with the host

< Maximum 1D layered texture width

< Maximum layers in a 1D layered texture

< Deprecated, do not use.

< Maximum 2D texture width if CUDA_ARRAY3D_TEXTURE_GATHER is set

< Maximum 2D texture height if CUDA_ARRAY3D_TEXTURE_GATHER is set

< Alternate maximum 3D texture width

< Alternate maximum 3D texture height

< Alternate maximum 3D texture depth

< PCI domain ID of the device

< Pitch alignment requirement for textures

< Maximum cubemap texture width/height

< Maximum cubemap layered texture width/height

< Maximum layers in a cubemap layered texture

< Maximum 1D surface width

< Maximum 2D surface width

< Maximum 2D surface height

< Maximum 3D surface width

< Maximum 3D surface height

< Maximum 3D surface depth

< Maximum 1D layered surface width

< Maximum layers in a 1D layered surface

< Maximum 2D layered surface width

< Maximum 2D layered surface height

< Maximum layers in a 2D layered surface

< Maximum cubemap surface width

< Maximum cubemap layered surface width

< Maximum layers in a cubemap layered surface

< Maximum 1D linear texture width

< Maximum 2D linear texture width

< Maximum 2D linear texture height

< Maximum 2D linear texture pitch in bytes

< Maximum mipmapped 2D texture width

< Maximum mipmapped 2D texture height

< Major compute capability version number

< Minor compute capability version number

< Maximum mipmapped 1D texture width

< Device supports stream priorities

< Device supports caching globals in L1

< Device supports caching locals in L1

< Maximum shared memory available per multiprocessor in bytes

< Maximum number of 32-bit registers available per multiprocessor

< Device can allocate managed memory on this system

< Device is on a multi-GPU board

< Unique id for a group of devices on the same multi-GPU board

< Link between the device and the host supports native atomic operations (this is a placeholder attribute, and is not supported on any current hardware)

< Ratio of single precision performance (in floating-point operations per second) to double precision performance

< Device supports coherently accessing pageable memory without calling cudaHostRegister on it

< Device can coherently access managed memory concurrently with the CPU

< Device supports compute preemption.

< Device can access host registered memory at the same virtual address as the CPU

< ::cuStreamBatchMemOp and related APIs are supported.

< 64-bit operations are supported in ::cuStreamBatchMemOp and related APIs.

< ::CU_STREAM_WAIT_VALUE_NOR is supported.

< Device supports launching cooperative kernels via ::cuLaunchCooperativeKernel

< Device can participate in cooperative kernels launched via ::cuLaunchCooperativeKernelMultiDevice

< Maximum optin shared memory per block

< Both the ::CU_STREAM_WAIT_VALUE_FLUSH flag and the ::CU_STREAM_MEM_OP_FLUSH_REMOTE_WRITES MemOp are supported on the device. See \ref CUDA_MEMOP for additional details.

< Device supports host memory registration via ::cudaHostRegister.

< Device accesses pageable memory via the host's page tables.

< The host can directly access managed memory on the device without migration.